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ltc3851a-1 1 3851a1fa typical a pplica t ion fea t ures a pplica t ions descrip t ion synchronous step-down switching regulator controller the ltc ? 3851a-1 is a high performance synchronous step-down switching regulator controller that drives an all n-channel synchronous power mosfet stage. a con stant frequency current mode architecture allows a phase - lockable frequency of up to 750khz. o pti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. the ltc3851a-1 features a precision 0.8v reference and a power good indicator. a wide 4v to 38v (40v absolute maximum) input supply range encompasses most battery confgurations and intermediate bus voltages. the tk/ss pin ramps the output voltage during start - up and shutdown with coincident or ratiometric tracking. current foldback limits mosfet heat dissipation during short- circuit conditions. the mode/pllin pin selects among burst mode operation, pulse-skipping mode or continu- ous inductor current mode at light loads and allows the ic to be synchronized to an external clock. the ltc3851a-1 contains an improved pll compared to the ltc3851-1. the ltc3851a-1 is identical to the ltc3851a except that the i lim pin is replaced by pgood. high effciency synchronous step-down converter n wide v in range: 4v to 38v operation n r sense or dcr current sensing n 1% output voltage accuracy n power good output voltage monitor n phase-lockable fixed frequency: 250khz to 750khz n dual n-channel mosfet synchronous drive n very low dropout operation: 99% duty cycle n adjustable output voltage soft-start or t racking n output current foldback limiting n output overvoltage protection n opti-loop ? compensation minimizes c out n selectable continuous, pulse-skipping or burst mode ? operation at light loads n low shutdown i q : 20a n v out range: 0.8v to 5.5v n thermally enhanced 16-lead msop or 3mm 3mm qfn package n automotive systems n telecom systems n industrial equipment n distributed dc power systems effciency and power loss vs load current l , lt, ltc, ltm, burst mode, opti-loop, linear technology and the linear logo are registered trademarks and no r sense , ultrafast are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5408150, 5481178, 5705919, 5929620, 6304066, 6498466, 6580258, 6611131. pgo0d run tk/ss i th freq/pllfltr v in intv cc tg sw intv cc mode/pllin bg sense + sense ? v fb gnd 0.047f 0.1f 4.7f 3.01k ltc3851a-1 22f v in 4.5v to 38v v out 3.3v 15a 3851a1 ta01a 0.68h 330pf 2200pf 0.1f 0.1f 330f 2 boost 15k 154k 48.7k 30.1k 82.5k 100k load current (ma) 10 70 efficiency (%) power loss (mw) 75 80 85 90 100 1000 10000 100000 3851a1 ta01b 65 60 55 50 95 100 1000 100 10 10000 v in = 12v v out = 3.3v efficiency power loss
ltc3851a-1 2 3851a1fa a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ......................... 40 v to C0.3v topside driver voltage (boost) ................ 4 6v to C0.3v switch voltage (sw) ..................................... 4 0v to C5v intv cc , (boost C sw), run, pgood ........ 6v to C0.3v tk/ss ................................................... in tv cc to C0.3v sense + , sense C .......................................... 6v to C0.3v mode/pllin, freq/pllfltr .............. in tv cc to C0.3v i th , v fb voltages ......................................... 3v to C0.3v (note 1) 1 2 3 4 5 6 7 8 mode/pllin freq/pllfltr run tk/ss i th fb sense ? sense + 16 15 14 13 12 11 10 9 sw tg boost v in intv cc bg gnd pgood top view 17 gnd mse package 16-lead plastic msop t jmax = 125c, ja = 35c/w to 40c/w exposed pad (pin 17) is gnd, must be soldered to pcb 16 15 14 13 5 6 7 8 top view 17 gnd ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1run tk/ss i th fb boost v in intv cc bg freq/pllfltr mode/pllin sw tg sense ? sense + pgood gnd t jmax = 125c, ja = 68c/w, jc = 4.2c/w exposed pad (pin 17) is gnd, must be soldered to pcb p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc3851aemse-1#pbf ltc3851aemse-1#trpbf 3851a1 16-lead plastic msop C40c to 125c ltc3851aimse-1#pbf ltc3851aimse-1#trpbf 3851a1 16-lead plastic msop C40c to 125c ltc3851ahmse-1#pbf ltc3851ahmse-1#trpbf 3851a1 16-lead plastic msop C40c to 150c ltc3851ampmse-1#pbf ltc3851ampmse-1#trpbf 3851a1 16-lead plastic msop C55c to 150c ltc3851aeud-1#pbf ltc3851aeud-1#trpbf lfqb 16-lead (3mm 3mm) plastic qfn C40c to 125c ltc3851aiud-1#pbf ltc3851aiud-1#trpbf lfqb 16-lead (3mm 3mm) plastic qfn C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ intv cc peak output current .................................. 50m a operating junction temperature range (notes 2, 3) e-grade, i-grade ................................ C 40c to 125c h-grade ............................................. C 40c to 150c mp-grade .......................................... C 55c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) m se .................................................................. 3 00c
ltc3851a-1 3 3851a1fa e lec t rical c harac t eris t ics symbol parameter conditions min typ max units main control loops v in input operating voltage range 4 38 v v fb regulated feedback voltage i th = 1.2v (note 4) 0c to 85c i th = 1.2v (note 4) C40c to 125c i th = 1.2v (note 4) C40c to 150c i th = 1.2v (note 4) C55c to 150c l l l l 0.792 0.788 0.788 0.788 0.800 0.808 0.812 0.812 0.812 v v v v i fb feedback current (note 4) C10 C50 na v reflnreg reference voltage line regulation v in = 6v to 38v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop, ?i th = 1.2v to 0.7v (note 4) measured in servo loop, ?i th = 1.2v to 0.7v (h-grade, mp-grade) l l 0.01 0.1 0.2 % % (note 4) measured in servo loop, ?i th = 1.2v to 1.6v (note 4) measured in servo loop, ?i th = 1.2v to 1.6v (h-grade, mp-grade) l l C0.01 C0.1 C0.2 % % g m transconductance amplifer g m i th = 1.2v, sink/source = 5a (note 4) 2 mmho g m gbw transconductance amp gain bandwidth i th = 1.2v (note 8) 3 mhz i q input dc supply current normal mode shutdown (note 5) v run = 5v v run = 0v 1 25 50 ma a uvlo undervoltage lockout on intv cc v intvcc ramping down 3.25 v uvlo hys uvlo hysteresis 0.4 v i sense sense pins current 1 2 a i tk/ss soft-start charge current v tk/ss = 0v 0.6 1 2 a v run run pin onthreshold v run rising l 1.10 1.22 1.35 v v runhys run pin onhysteresis 120 mv v sense(max) maximum current sense threshold v fb = 0.7v, v sense = 3.3v v fb = 0.7v, v sense = 3.3v (h-grade, mp-grade) l l 40 35 53 65 70 mv mv tg r up tg driver pull-up on-resistance tg high 2.2 tg r down tg driver pull-down on-resistance tg low 1.2 bg r up bg driver pull-up on-resistance bg high 2.1 bg r down bg driver pull-down on-resistance bg low 1.1 tg t r tg t f tg transition time rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg tr bg tf bg transition time rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns tg/bg t 1d top gate off to bottom gate on delay bottom switch-on delay time c load = 3300pf each driver (note 6) 30 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver (note 6) 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 38v 4.8 5 5.2 v v ldo int intv cc load regulation i cc = 0ma to 50ma 0.5 % the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise noted.
ltc3851a-1 4 3851a1fa e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the specifed operating junction temperature range, otherwise specifcations are at t a = 25c (note 2). v in = 15v, v run = 5v unless otherwise noted. symbol parameter conditions min typ max units oscillator and phase-locked loop f nom nominal frequency r freq = 60k 460 500 540 khz f low lowest frequency r freq = 160k 205 235 265 khz f high highest frequency r freq = 36k 690 750 810 khz r mode/pllin mode/pllin input resistance 100 k f mode mode/pllin minimum input frequency mode/pllin maximum input frequency v mode = external clock v mode = external clock 250 750 khz khz i freq phase detector output current sinking capability sourcing capability f mode > f osc f mode < f osc C90 75 a a pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative (uv) v fb ramping positive (ov) C12.5 7.5 C10 10 C7.5 12.5 % % note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3851a-1 is tested under pulsed load conditions such that t a t j . the ltc3851ae-1 is guaranteed to meet performance speci f cations from 0c to 85c junction temperature. speci f cations over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the l tc3851ai-1 is guaranteed to meet specifcations over the C40c to 125c operating junction temperature range, the ltc3851ah-1 is guaranteed over the C40c to 150c operating junction temperature range and the ltc3851amp-1 is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note that the maximum ambient temperature consistent with these specifcations is determined by specifc operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: ltc3851amse-1: t j = t a + (p d ? 40c/w) ltc3851aud-1: t j = t a + (p d ? 68c/w) note 4: the ltc3851a-1 is tested in a feedback loop that servos v ith to a speci f ed voltage and measures the resultant v fb . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. rise and fall times are assured by design, characterization and correlation with statistical process controls. note 7: the minimum on-time condition is speci f ed for an inductor peak-to-peak ripple current ~40% of i max (see minimum on-time considerations in the applications information section). note 8: guaranteed by design; not tested in production.
ltc3851a-1 5 3851a1fa typical p er f or m ance c harac t eris t ics load step (burst mode operation) load step (forced continuous mode) effciency vs output current and mode effciency vs output current and mode effciency and power loss vs input voltage effciency vs output current and mode i load 5a/div 0.2a to 7.5a v out 100mv/div ac-coupled i l 5a/div 100s/div v out = 1.5v v in = 12v figure 11 circuit 3851a1 g05 i load 5a/div 0.2a to 7.5a v out 100mv/div ac-coupled i l 5a/div 100s/div v out = 1.5v v in = 12v figure 11 circuit 3851a1 g06 load current (ma) 10 40 efficiency (%) 50 60 70 80 100 1000 10000 100000 3851a1 g03 30 20 10 0 90 100 v in = 12v v out = 5v burst ccm pulse skip input voltage (v) 4 70 efficiency (%) power loss (mw) 75 85 90 95 12 20 24 32 3851a1 g04 80 8 16 28 100 100 1000 10000 v in = 12v v out = 3.3v figure 11 circuit power loss, i out = 5a power loss, i out = 0.5a efficiency, i out = 0.5a efficiency, i out = 5a load current (ma) 10 40 efficiency(%) 50 60 70 80 100 1000 10000 100000 3851a1 g01 30 20 10 0 90 100 v in = 12v v out = 1.5v burst ccm pulse skip load current (ma) 10 40 efficiency(%) 50 60 70 80 100 1000 10000 100000 3851a1 g02 30 20 10 0 90 100 v in = 12v v out = 3.3v figure 11 circuit burst ccm pulse skip
ltc3851a-1 6 3851a1fa typical p er f or m ance c harac t eris t ics load step (pulse-skipping mode) inductor current at light load start-up with prebiased output at 2v coincident tracking with master supply ratiometric tracking with master supply input dc supply current vs input voltage i load 5a/div 0.2a to 7.5a v out 100mv/div ac-coupled i l 5a/div 100s/div v out = 1.5v v in = 12v figure 11 circuit 3851a1 g07 forced continous mode 5a/div pulse skip mode 5a/div burst mode operation 5a/div 1s/div v out = 1.5v v in = 12v i load = 1ma figure 11 circuit 3851a1 g08 v out 2v/div v fb 0.5v/div 20ms/div 3851a1 g09 tk/ss 0.5v/div 10ms/div 3851a1 g10 v master 0.5v/div v out 2a load 0.5v/div v master 0.5v/div v out 2a load 0.5v/div 10ms/div 3851a1 g11 input voltage (v) 4 supply current (ma) 12 20 24 40 3851a1 g12 8 16 28 32 36 3.0 2.5 2.0 1.5 1.0 0.5 0
ltc3851a-1 7 3851a1fa typical p er f or m ance c harac t eris t ics maximum current sense threshold vs common mode voltage maximum peak current sense threshold vs i th voltage burst mode peak current sense threshold vs i th voltage maximum current sense threshold vs duty cycle regulated feedback voltage vs temperature intv cc line regulation shutdown (run) threshold vs temperature maximum current sense threshold vs feedback voltage (current foldback) tk/ss pull-up current vs temperature temperature (c) ?75 ?50 0.5 tk/ss current (a) 0.6 0.8 0.9 1.0 1.5 1.2 0 50 75 3851a1 g19 0.7 1.3 1.4 1.1 ?25 25 100 125 150 temperature (c) ?75 ?50 ?25 0.9 run pin voltage (v) 1.1 1.4 0 50 75 3851a1 g20 1.0 1.3 1.2 25 100 150125 run rising threshold (on) run falling threshold (off) temperature (c) ?75 ?50 regulated feedback voltage (mv) 802 804 806 25 75 3851a1 g21 800 798 ?25 0 50 100 150125 796 794 input voltage (v) 4 8 12 3.5 intv cc voltage (v) 3.7 4.1 4.3 4.5 28 32 36 5.3 3851a1 g13 3.9 16 20 24 40 4.7 4.9 5.1 i load = 0ma i load = 25ma v sense common mode voltage (v) 0 0 v sense threshold (mv) 3 3.5 4 4.5 90 80 70 60 50 40 30 20 10 3851a1 g14 0.5 1 1.5 2 2.5 5 v ith (v) 0 0.2 0.4 0.6 v sense (mv) 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 3851a1 g15 2.4 90 80 70 60 50 40 30 20 10 0 ?10 ?20 duty cycle range: 0% to 100% v ith (v) v sense (mv) 60 50 40 30 20 10 0 0.8 1.2 1.6 2.0 3851a1 g16 2.4 0.60.4 1.0 1.4 1.8 2.2 burst comparator falling theshold: v ith = 0.4v maximuim minimuim duty cycle (%) 0 0 current sense threshold (mv) 10 30 40 50 40 80 100 90 3851a1 g17 20 20 60 60 70 80 feedback voltage (v) 0 maximum v sense (mv) 0.8 3851a1 g18 0 0.2 0.4 0.6 0.1 0.3 0.5 0.7 90 80 70 60 50 40 30 20 10
ltc3851a-1 8 3851a1fa oscillator frequency vs temperature undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage typical p er f or m ance c harac t eris t ics shutdown input dc supply current vs input voltage shutdown input dc supply current vs temperature input dc supply current vs temperature input voltage (v) 0 shutdown supply current (a) 20 30 40 3851a1 g25 10 0 10 20 30 5 15 25 35 40 15 25 5 35 maximum current sense threshold vs intv cc voltage intv cc voltage(v) 3.2 3.4 3.6 0 current sense threshold (mv) 10 30 40 50 4.4 4.6 4.8 90 3851a1 g28 20 3.8 4.0 4.2 5.0 60 70 80 temperature (c) ?75 ?50 600 700 900 25 75 3851a1 g22 500 400 ?25 0 50 100 150125 300 200 800 frequency (khz) r plllpf = 36k r plllpf = 60k r plllpf = 160k temperature (c) ?75 ?50 ?25 0 intv cc voltage at uvlo threshold (v) 2 5 0 50 75 3851a1 g24 1 4 3 25 100 150125 intv cc ramping up intv cc ramping down temperature (c) ?75 ?50 shutdown input dc supply current (a) 35 25 3851a1 g26 20 10 ?25 0 50 5 0 40 30 25 15 75 100 150125 temperature (c) ?75 ?50 input dc supply current (ma) 2.0 2.5 3.0 25 75 3851a1 g27 1.5 1.0 ?25 0 50 100 150125 0.5 0 input voltage (v) 5 frequency (khz) 415 20 3851a1 g23 400 390 10 15 25 385 380 420 410 405 395 30 35 40 r freq = 80k
ltc3851a-1 9 3851a1fa p in func t ions (mse/ud) mode/pllin (pin 1/pin 15): forced continuous mode, burst mode or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to intv cc to force continuous conduction mode of operation. connect to gnd to enable pulse-skip- ping mode of operation. to select burst mode operation, tie this pin to intv cc through a resistor no less than 50k, but no greater than 250k. a clock on the pin will force the controller into forced continuous mode of operation and synchronize the internal oscillator. freq/pllfltr (pin 2/pin 16): the phase-locked loops lowpass flter is tied to this pin. alternatively, a resistor can be connected between this pin and gnd to vary the frequency of the internal oscillator. run (pin 3/pin 1): run control input. a voltage above 1.22v on this pin turns on the ic. however, forcing this pin below 1.1v causes the ic to shut down the ic. there is a 2a pull-up current on this pin. tk/ss (pin 4/pin 2): output voltage tracking and soft-start input. a capacitor to ground at this pin sets the ramp rate for the output voltage. an internal soft-start current of of 1a charges this capacitor. i th (pin 5/pin 3): current control threshold and error amplifer compensation point. the current comparator tripping threshold increases with its i th control voltage. fb (pin 6/pin 4): error amplifer feedback input. this pin receives the remotely sensed feedback voltage from an external resistive divider across the output. sense C (pin 7/pin 5): current sense comparator inverting input. the (C) input to the current comparator is connected to the output. sense + (pin 8/pin 6): current sense comparator non- inverting input. the (+) input to the current comparator is normally connected to the dcr sensing network or current sensing resistor. pgood (pin 9/pin 7): power good indicator output. open- drain logic out that is pulled to ground when the output voltage exceeds the 10% regulation window, after the internal 17s power bad mask timer expires. gnd (pin 10/pin 8, exposed pad pin 17): ground. all small-signal components and compensation components should be kelvin connected to this ground. the (C) terminal of cv cc and the (C) terminal of c in should be closely con- nected to this pin. the exposed pad should be soldered to ground for good thermal conductivity. bg (pin 11/pin 9): bottom gate driver output. this pin drives the gate of the bottom n-channel mosfet between gnd and intv cc . intv cc (pin 12/pin 10): internal 5v regulator output. the control circuit is powered from this voltage. decouple this pin to gnd with a minimum 2.2f low esr tantalum or ceramic capacitor. v in (pin 13/pin 11): main input supply. decouple this pin to gnd with a capacitor. boost (pin 14/pin 12): boosted floating driver supply. the (+) terminal of the boost-strap capacitor is connected to this pin. this pin swings from a diode voltage drop below intv cc up to v in + intv cc . tg (pin 15/pin 13): top gate driver output. this is the output of a foating driver with a voltage swing equal to intv cc superimposed on the switch node voltage. sw (pin 16/pin 14): switch node connection to the in- ductor. voltage swing at this pin is from a schottky diode (external) voltage drop below ground to v in .
ltc3851a-1 10 3851a1fa func t ional diagra m ? + ? + ? + ? + v in 2a slope compensation uvlo osc s rq 5k run switch logic and anti- shoot through bg on pulse skip 0.8v ov 1 100k 1.22v 0.64v i th r c intv cc i thb i cmp c c1 ea ss r1 0.88v r2 run gnd intv cc i rev sw tg c b v in c in v in sleep boost bursten ? + ? + uv ov c vcc v out c out m2 m1 l1 d b mode/pllin 100k sense + sense ? ? + 0.8v ref tk/ss run 0.4v ? + v fb freq/pllfltr pll-sync 5v reg mode/sync detect + + 1a c ss + pgood ? + 0.72v 3851a1 fd
ltc3851a-1 11 3851a1fa o pera t ion main control loop the ltc3851a-1 is a constant frequency, current mode step-down controller. during normal operation, the top mosfet is turned on when the clock sets the rs latch, and is turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of the error ampli fer, ea. the v fb pin receives the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.8v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse current comparator, i rev , or the beginning of the next cycle. intv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. an internal 5v low dropout linear regulator supplies intv cc power from v in . the top mosfet driver is biased from the foating boot - strap capacitor, c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detec tor detects this and forces the top mosfet off for about 1/10 of the clock period every tenth cycle to allow c b to recharge. however, it is recommended that there is always a load present during the drop-out transition to ensure c b is recharged. shutdown and start-up (run and tk/ss) the ltc3851a-1 can be shut down using the run pin. pulling this pin below 1.1v disables the controller and most of the internal circuitry, including the intv cc regula- tor. releasing the run pin allows an internal 2a current to pull up the pin and enable that controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of the controllers output voltage, v out , is controlled by the voltage on the tk/ss pin. when the voltage on the tk/ss pin is less than the 0.8v internal reference, the ltc3851a-1 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.8v reference. this allows the tk/ss pin to be used to program a soft-start by connecting an external capacitor from the tk/ss pin to gnd. an internal 1a pull-up current charges this capacitor creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.8v (and beyond), the output voltage v out rises smoothly from zero to its fnal value. alternatively, the tk/ss pin can be used to cause the start-up of v out to track another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground (see the applica tions information section). when the run pin is pulled low to disable the controller, or when int v cc drops below its undervoltage lockout threshold of 3.2v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, the controller is disabled and the external mosfets are held off. light load current operation (burst mode operation, pulse-skipping or continuous conduction) the ltc3851a-1 can be enabled to enter high effciency burst mode operation, constant frequency pulse-skipping mode or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to intv cc . to select pulse-skipping mode of operation, foat the mode/pllin pin or tie it to gnd. to select burst mode operation, tie mode/pllin to intv cc through a resistor no less than 50k, but no greater than 250k. when the controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-forth of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifer, ea, will decrease the voltage on the i th pin. when the i th voltage drops below 0.4v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off.
ltc3851a-1 12 3851a1fa o pera t ion in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator, i rev , turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from revers - ing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur - rent is determined by the voltage on the i th pin, just as in normal operation. in this mode the effciency at light loads is lower than in burst mode operation. however, continu - ous mode has the advantages of lower output ripple and less interference to audio circuitry. when the mode/pllin pin is connected to gnd, the ltc3851a-1 operates in pwm pulse-skipping mode at light loads. at very light loads the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current effciency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq/pllfltr and mode/pllin pins) the selection of switching frequency is a trade-off between effciency and component size. low frequency operation increases effciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to main - tain low output ripple voltage. the switching frequency of the ltc3851a-1 can be selected using the freq/pllfl tr pin. if the mode/pllin pin is not being driven by an ex- ternal clock source, the freq/pllfltr pin can be used to program the controllers operating frequency from 250khz to 750khz. a phase-locked loop (pll) is available on the ltc3851a-1 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller operates in forced continuous mode of operation when it is synchronized. a series rc should be connected between the freq/pllfltr pin and gnd to serve as the plls loop flter. it is suggested that the external clock be applied before enabling the controller unless a second resistor is con- nected in parallel with the series rc loop flter network. the second resistor prevents low switching frequency operation if the controller is enabled before the clock. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious con - ditions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. power good (pgood) pin the pgood pin is connected to an open drain of an internal n-channel mosfet. the mosfet turns on and pulls the pgood pin low when the v fb pin voltage is not within 10% of the 0.8v reference voltage. the pgood pin is also pulled low when the run pin is low (shut down) or when the ltc3851a-1 is in the soft-start or tracking phase. when the v fb pin voltage is within the 10% requirement, the mosfet is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6v. the pgood pin will fag power good immediately when the v fb pin is within the 10% window. however, there is an internal 17s power bad mask when v fb goes out of the 10% window.
ltc3851a-1 13 3851a1fa a pplica t ions i n f or m a t ion the typical application on the frst page of this data sheet is a basic ltc3851a-1 application circuit. the ltc3851a-1 can be confgured to use either dcr (inductor resistance) sensing or low value resistor sensing. the choice of the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resis tors and is more power effcient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller . other external component selection is driven by the load require ment, and begins with the selection of r sense (if r sense is used) and the inductor value. next, the power mosfets and schottky diodes are selected. finally, input and output capacitors are selected. the circuit shown on the frst page can be confgured for operation up to 38v at v in . sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 5.5v. both sense pins are high impedance inputs with small base currents of less than 1a. when the sense pins ramp up from 0v to 1.4v, the small base currents fow out of the sense pins. when the sense pins ramp down from 5v to 1.1v, the small base currents fow into the sense pins. the high impedance inputs to the current comparators allow accurate dcr sensing. however, care must be taken not to foat these pins during normal operation. low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 1. r sense is chosen based on the required output current. the current comparator has a maximum threshold, v max = 53mv. the current comparator threshold sets the maximum peak of the inductor current, yielding a maximum average output current, i max , equal to the peak value less half the peak-to-peak ripple current, ? i l . allowing a margin of 20% for variations in the ic and external component values yields: r sense = 0.8 ? v max i max + ?i l /2 inductor dcr sensing for applications requiring the highest possible effciency, the ltc3851a-1 is capable of sensing the voltage drop across the inductor dcr, as shown in figure 2. the dcr of the inductor represents the small amount of dc winding resis tance of the copper, which can be less than 1m for todays low value, high current inductors. if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the voltage drop across the inductor dcr multiplied by r2/(r1 + r2). therefore, r2 may be used to scale the voltage across the sense terminals when the dcr is greater than the target sense resistance. check the manufacturers data sheet for specifcations regarding the inductor dcr, in order to properly dimension the external flter components. the dcr of the inductor can also be measured using a good rlc meter. figure 1. using a resistor to sense current with the ltc3851a-1 v in v in intv cc boost tg sw bg gnd filter components placed near sense pins sense + sense ? ltc3851a-1 v out r sense 3851a1 f01
ltc3851a-1 14 3851a1fa a pplica t ions i n f or m a t ion figure 2. current mode control using the inductor dcr slope compensation and inductor peak current slope compensation provides stability in constant fre- quency architectures by preventing sub-harmonic oscil - lations at high duty cycles. it is accomplished inter nally by adding a compensating ramp to the inductor current signal. normally, this results in a reduction of maximum inductor peak cur rent for duty cycles >40%. however, the l tc3851a-1 uses a novel scheme that allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values. a higher frequency generally results in lower effciency because of mosfet gate charge losses. in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered. the inductor value has a direct effect on ripple current. the inductor ripple current ?i l decreases with higher inductance or frequency and increases with higher v in : ?i l = 1 f ? l v out 1C v out v in ? ? ? ? ? ? accepting larger values of ?i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses. a reasonable starting point for setting ripple current is ?i l = 0.3(i max ). the maximum ?i l occurs at the maximum input voltage. the inductor value also has secondary effects. the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 10% of the current limit determined by r sense . lower inductor values (higher ?i l ) will cause this to occur at lower load currents, which can cause a dip in effciency in the upper range of low current operation. in burst mode operation, lower inductance values will cause the burst frequency to increase. inductor core selection once the value for l is known, the type of inductor must be selected. high effciency converters generally cannot afford the core loss found in low cost powdered iron cores, forcing the use of more expensive ferrite or molypermalloy cores. actual core loss is independent of core size for a fxed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con - centrate on copper loss and preventing saturation. ferrite core material saturates hard , which means that induc - tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfet s must be selected for the ltc3851a-1 controller: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. v in v in intv cc boost tg sw bg gnd inductor dcrl sense + sense ? ltc3851a-1 v out 3851a1 f02 r1 r2 *place c1 near sense + , sense ? pins c1* r1||r2 ? c1 = r sense(eq) = dcr l dcr r2 r1 + r2
ltc3851a-1 15 3851a1fa the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up. consequently, logic-level threshold mosfets must be used in most ap - plications. the only exception is if low input voltage is ex- pected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specifcation for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately fat divided by the specifed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specifed v ds . when the ic is operating in continuous mode, the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in C v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v th(min) + 1 v th(min) ? ? ? ? ? ? ? ? (f) p sync = v in C v out v in i max ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2 ) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which are highest at high input voltages. for v in < 20v, the high current effciency generally improves with larger mosfets, while for v in > 20v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher effciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diode conducts during the dead time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turn- ing on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in effciency at high v in . a 1a to 3a schottky is generally a good size due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. soft-start and tracking the ltc3851a-1 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when the ltc3851a-1 is confgured to soft-start by itself, a capacitor should be connected to the tk/ss pin. the ltc3851a-1 is in the shutdown state if the run pin voltage is below 1.10v. tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.22v, the ltc3851a-1 powers up. a soft-start current of 1a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is a pplica t ions i n f or m a t ion
ltc3851a-1 16 3851a1fa 0v to 0.8v on the tk/ss pin. the total soft-start time can be calculated as: t soft-start = 0.8 ? c ss 1.0a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.64v. between tk/ss = 0.64v and 0.72v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.72v. the output ripple is minimized during the 80mv forced continuous mode window. when the regulator is confgured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always fowing, producing a small offset error. to minimize this error, one can select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another supply after the soft-start phase expires, the ltc3851a-1 must be confgured for forced continuous operation by connecting mode/pllin to intv cc . output voltage tracking the ltc3851a-1 allows the user to program how its output ramps up and down by means of the tk/ss pins. through this pin, the output can be set up to either co- incidentally or ratiometrically track with another supplys output, as shown in figure 3. in the following discussions, v master refers to a master supply and v out refers to the ltc3851a-1s output as a slave supply. to implement the coincident tracking in figure 3a, connect a resistor divider to v master and connect its midpoint to the tk/ss pin of the ltc3851a-1. the ratio of this divider should be selected the same as that of the ltc3851a-1s feedback divider as shown in figure 4a. in this tracking mode, v master must be higher than v out . to implement ratiometric tracking, the ratio of the resistor divider connected to v master is determined by: v out v master = r2 r4 r3 + r4 r1 + r2 ? ? ? ? ? ? so which mode should be programmed? while either mode in figure 4 satisfes most practical applications, the coincident mode offers better output regulation. this concept can be better understood with the help of figure 5. at the input stage of the ltc3851a-1 s error amplifer, two common anode diodes are used to clamp a pplica t ions i n f or m a t ion figure 3. two different modes of output voltage tracking time (3a) coincident tracking v master v out output voltage v master v out time 3851a1 f03 (3b) ratiometric tracking output voltage 3851a13851a1
ltc3851a-1 17 3851a1fa a pplica t ions i n f or m a t ion the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same amplitude. in the coincident mode, the tk/ss voltage is substantially higher than 0.8v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb and the internal precision 0.8v reference. in the ratiometric mode, however, tk/ss equals 0.8v at steady state. d1 will divert part of the bias current to make v fb slightly lower than 0.8v. although this error is minimized by the exponential i-v characteristic of the diode, it does impose a fnite amount of output voltage deviation. furthermore, when the master supplys output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. intv cc regulator the ltc3851a-1 features a pmos low dropout linear regula tor (ldo) that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the ltc3851a-1 s internal circuitry. the ldo regulates the voltage at the intv cc pin to 5v. the ldo can supply a peak current of 50ma and must be bypassed to ground with a minimum of 2.2f ceramic capacitor or low esr electrolytic capacitor. no matter what type of bulk capaci tor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the int v cc and gnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3851a-1 to be exceeded. the int v cc current, which is dominated by the gate charge current, is supplied by the 5v ldo. power dissipation for the ic in this case is highest and is approximately equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the effciency considerations section. the junction tem- perature can be estimated by using the equa tions given in note 3 of the electrical characteristics. for example, the ltc3851a-1 intv cc current is limited to less than 17ma from a 36v supply in the gn package: t j = 70c + (17ma)(36v)(90c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (mode/pllin = intv cc ) at maximum v in . topside mosfet driver supply (c b , d b ) an external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltage for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin figure 4. setup for coincident and ratiometric tracking figure 5. equivalent input circuit of error amplifer r3 v out r4 (4a) coincident tracking setup to v fb pin r3 v master r4 to tk/ss pin r1 r3 v out r4 r2 3851a1 f04 (4b) ratiometric tracking setup to v fb pin to tk/ss pin v master ? + i i d1 tk/ss 0.8v v fb d2 d3 3851a1 f05 ea
ltc3851a-1 18 3851a1fa a pplica t ions i n f or m a t ion is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc the value of the boost capacitor, c b , needs to be 100 times that of the total input capa citance of the topside mosfet. the reverse break down of the external schottky diode must be greater than v in(max) . undervoltage lockout the ltc3851a-1 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.2v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 400mv of preci - sion hysteresis. another way to detect an undervoltage condition is to moni - tor the v in supply. because the run pin has a precision turn-on reference of 1.22v, one can use a resistor divider to v in to turn on the ic when v in is high enough. c in selection in continuous mode, the source current of the top n-chan - nel mosfet is a square wave of duty cycle v out /v in . to prevent large voltage transients, a low esr input capacitor sized for the maximum rms current must be used. the maximum rms capacitor current is given by: i rms ? i o(max) v out v in v in v out C 1 ? ? ? ? ? ? 1/ 2 this formula has a maximum at v in = 2v out , where i rms = i o(max) /2. this simple worst-case condition is com monly used for design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. always consult the manufacturer if there is any question. c out selection the selection of c out is primarily determined by the effec- tive series resistance, esr, to minimize voltage ripple. the output ripple, ? v out , in continuous mode is determined by: ?v out ?i l esr + 1 8fc out ? ? ? ? ? ? where f = operating frequency, c out = output capaci tance and ?i l = ripple current in the inductor. the output ripple is highest at maximum input voltage since ?i l increases with input voltage. typically, once the esr requirement for c out has been met, the rms current rating gener - ally far exceeds the i ripple(p-p) requirement. with ?i l = 0.3i out(max) and allowing 2/3 of the ripple to be due to esr, the output ripple will be less than 50mv at maximum v in and: c out required esr < 2.2r sense c out > 1 8fr sense the frst condition relates to the ripple current into the esr of the output capacitance while the second term guaran tees th at the output capacitance does not signifcantly discharge during the operating frequency period due to ripple current. the choice of using smaller output capaci tance increases the ripple voltage due to the discharging term but can be compensated for by using capacitors of very low esr to maintain the ripple voltage at or below 50mv. the i th pin opti-loop compensation compo nents can be optimized to provide stable, high per for mance transient response regardless of the output capaci tors selected. the selection of output capacitors for applications with large load current transients is primarily determined by the voltage tolerance specifcations of the load. the resistive component of the capacitor, esr, multiplied by the load current change, plus any output voltage ripple must be within the voltage tolerance of the load.
ltc3851a-1 19 3851a1fa a pplica t ions i n f or m a t ion the required esr due to a load current step is: r esr ?v ?i where ? i is the change in current from full load to zero load (or minimum load) and ? v is the allowed voltage devia- tion (not including any droop due to fnite capacitance). the amount of capacitance needed is determined by the maximum energy stored in the inductor. the capacitance must be suffcient to absorb the change in inductor current when a high current to low current transition occurs. the opposite load current transition is generally determined by the control loop opti-loop components, so make sure not to over compensate and slow down the response. the minimum capacitance to assure the inductors energy is adequately absorbed is: c out > l ?i ( ) 2 2 ?v ( ) v out where ?i is the change in load current. manufacturers such as nichicon, united chemi-con and sanyo can be considered for high performance through- hole capacitors. the os-con semiconductor electrolyte capacitor available from sanyo has the lowest (esr)(size) product of any aluminum electrolytic at a somewhat higher price. an additional ceramic capacitor in parallel with os-con capacitors is recommended to reduce the inductance effects. in surface mount applications, esr, rms current han dling and load step specifcations may require multiple capaci - tors in parallel. aluminum electrolytic, dry tantalum and special polymer capacitors are available in surface mount packages. special polymer surface mount capaci tors offer very low esr but have much lower capacitive density per unit volume than other capacitor types. these capacitors offer a ver y cost-effective output capacitor solution and are an ideal choice when combined with a controller having high loop bandwidth. tantalum capaci tors offer the highest capacitance density and are often used as output capaci - tors for switching regulators having controlled soft-start. several excellent surge-tested choices are the avx tps, avx tpsv or the kemet t510 series of surface mount tantalums, available in case heights rang ing from 1.5mm to 4.1mm. aluminum electrolytic capaci tors can be used in cost-driven applications, provided that consideration is given to ripple current ratings, tempera ture and long-term reliability. a typical application will require several to many aluminum electrolytic capacitors in parallel. a combina - tion of the above mentioned capaci tors will often result in maximizing per formance and minimizing overall cost. other capacitor types include nichicon pl series, nec neocap, panasonic sp and sprague 595d series. consult manufacturers for other specifc recommendations. like all components, capacitors are not ideal. each ca pacitor has its own benefts and limitations. combina - tions of different capacitor types have proven to be a very cost effective solution. remember also to include high frequency decoupling capacitors. they should be placed as close as possible to the power pins of the load. any inductance present in the circuit board traces negates their usefulness. setting output voltage the ltc3851a-1 output voltage is set by an external feed - back resistive divider carefully placed across the output, as shown in figure 6. the regulated output volt age is determined by: v out = 0.8v 1 + r b r a ? ? ? ? ? ? to improve the transient response, a feed-forward ca pacitor , c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. figure 6. settling output voltage ltc3851a-1 v fb v out r b c ff r a 3851a1 f06
ltc3851a-1 20 3851a1fa a pplica t ions i n f or m a t ion fault conditions: current limit and current foldback the ltc3851a-1 includes current foldback to help limit load current when the output is shorted to ground. if the output falls below 40% of its nominal output level, the maximum sense voltage is progressively lowered from its maximum programmed value to about 25% of the that value. foldback current limiting is disabled during soft-start or tracking. under short-circuit conditions with very low duty cycles, the ltc3851a-1 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time, t on(min) , of the ltc3851a-1 (90ns), the input voltage and inductor value: ?i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/4maxv sense r sense C 1 2 ?i l(sc) programming switching frequency to set the switching frequency of the ltc3851a-1, connect a resistor, r freq , between freq/pllfltr and gnd. the relationship between the oscillator frequency and r freq is shown in figure 7. a 0.1f bypass capacitor should be connected in parallel with r freq . phase-locked loop and frequency synchronization the ltc3851a-1 has a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (v co ) and a phase detector. this allows the turn-on of the top mosfet to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. this phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complemen - tary current sources that charge or discharge the external flter network connected to the freq/pllfltr pin. note that the ltc3851a-1 can only be synchronized to an external clock whose frequency is within range of the ltc3851a-1s internal v co .this is guaranteed to be be- tween 250khz and 750khz. a simplifed block diagram is shown in figure 8. if the external clock frequency is greater than the internal oscillators frequency, f osc , then current is sunk con - ti nuously from the phase detector output, pulling down the freq/pllfltr pin. when the external clock frequency is less than f osc , current is sourced continuously , pulling up the freq/pllfltr pin. if the external and internal frequen - cies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the freq/pllfltr pin is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the flter capacitor c lp holds the voltage. figure 7. relationship between oscillator frequency and resistor connected between freq/pllfltr and gnd figure 8. phase-locked loop block diagram r freq (k) 20 250 oscillator frequency (khz) 300 400 450 500 750 600 60 100 120 3851a1 f07 350 650 700 550 40 80 140 160 digital phase/ frequency detector vco 2.7v r lp c lp 3851a1 f08 freq/pllfltr external oscillator mode/ pllin
ltc3851a-1 21 3851a1fa a pplica t ions i n f or m a t ion the loop flter components, c lp and r lp , smooth out the current pulses from the phase detector and provide a stable input to the voltage-controlled oscillator. the flter components c lp and r lp determine how fast the loop acquires lock. typically r lp is 1k to 10k and c lp is 2200pf to 0.01f. when the external oscillator is active before the ltc3851 is enabled, the internal oscillator frequency will track the external oscillator frequency as described in the preceding paragraphs. in situations where the ltc3851 is enabled before the external oscillator is active, a low free-running oscillator frequency of approximately 50khz will result. it is possible to increase the free-running, pre-synchronization frequency by adding a second resistor, r freq , in parallel with r lp and c lp . r freq will also cause a phase difference between the internal and external oscillator signals. the magnitude of the phase difference is inversely proportional to the value r freq . the free-running frequency may be programmed by using figure 7 to determine the appropri- ate value of r freq . in order to maintain adequate phase margin for the pll, the typical value for c lp is 0.01f and the typical value for r lp is 1k. the external clock (on mode/pllin pin) input high threshold is nominally 1.6v, while the input low thres hold is nominally 1.2v. minimum on-t ime considerations minimum on-time, t on(min) , is the smallest time dura- tion that the ltc3851a-1 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in (f) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3851a-1 is approximately 90ns. however, as the peak sense voltage decreases the minimum on-time gradually increases. this is of particu - lar concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signifcant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. effciency considerations the per cent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3851a-1 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver current. v in current typi cally results in a small (<0.1%) loss. 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor and current sense resistor. in continuous mode, the average output current fows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet.
ltc3851a-1 22 3851a1fa a pplica t ions i n f or m a t ion if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to obtain i 2 r losses. for example, if each r ds(on) = 10m , dcr = 10m and r sense = 5m, then the total resis- tance is 25m. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. effciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become signifcant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: transition loss = (1.7)v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and the battery internal resistance can account for an additional 5% to 10% effciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has ad - equate charge storage and very low esr at the switch ing frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a maximum of 20m to 50m of esr. other losses including schottky con- duction losses during dead time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-fltered closed-loop response test point. the dc step, rise time and settling at this test point truly refects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the fltered and compensated control loop response. the midband gain of the loop will be in creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance.
ltc3851a-1 23 3851a1fa a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc3851a-1. these items are also illustrated graphically in the layout diagram of figure 9. check the following in your layout: 1. are the board signal and power grounds segregated? the ltc3851a-1 gnd pin should tie to the ground plane close to the input capacitor(s). the low current or signal ground lines should make a single point tie directly to the gnd pin. the synchronous mosfet sour ce pins should connect to the input capacitor(s) ground. a pplica t ions i n f or m a t ion figure 9. ltc3851a-1 layout diagram 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 mode/pllin freq/pllfltr run tk/ss i th v fb sense ? sense + sw tg boost v in intv cc bg gnd pgood ltc3851a-1 47pf c c c ss 0.1mf c c2 r freq r c r pgood 1000pf + c out r1 r2 c b d b r sense d1 m2 + 4.7f v pull-up m1 + c in + ? ? l1 v in + v out 3851a1 f09
ltc3851a-1 24 3851a1fa a pplica t ions i n f or m a t ion 2. does the v fb pin connect directly to the feedback resis- tors? the resistive divider r1, r2 must be connected between the (+) plate of c out and signal ground. the 47pf to 100pf capacitor should be as close as possible to the ltc3851a-1. be careful locating the feedback resistors too far away from the ltc3851a-1. the v fb line should not be routed close to any other nodes with high slew rates. 3. are the sense C and sense + leads routed together with minimum pc trace spacing? the flter capacitor between sense + and sense C should be as close as possible to the ltc3851a-1. ensure accurate current sensing with kelvin connections as shown in figure 10. series resistance can be added to the sense lines to increase noise rejection and to compensate for the esl of r sense . 4. does the (+) terminal of c in connect to the drain of the topside mosfet(s) as closely as possible? this capacitor provides the ac current to the mosfet(s). 5. is the intv cc decoupling capacitor connected closely between intv cc and gnd? this capacitor carries the mosfet driver peak currents. an addi tional 1f ceramic capacitor placed immediately next to the int v cc and gnd pins can help improve noise performance. 6. keep the switching node (sw), top gate node (tg) and boost node (boost) away from sensitive small-signal nodes, especially from the voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side (pin 9 to pin 16) of the l tc3851a-1 and occupy minimum pc trace area. pc board layout debugging it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main- tained over the input voltage range down to dropout and until the output load drops below the low current opera- tion thresholdtypically 10% of the maximum designed cur rent level in burst mode operation. th e duty cycle percentage should be maintained from cycle to cycle in a well designed, low noise pcb imple mentation. variation in the duty cycle at a subharmonic rate can sug - gest noise pick-up at the current or voltage sensing inputs or inadequate loop compensation. overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw , tg and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , the schottky and the top mosfet to the sensitive current and voltage sens- ing traces. in addition, investigate common ground path voltage pickup between these components and the gnd pin of the ic. figure 10. kelvin sensing r sense sense + sense ? high current path 3851a1 f10 current sense resistor (r sense )
ltc3851a-1 25 3851a1fa design example as a design example, assume v in = 12v (nominal), v in = 22v (maximum), v out = 1.8v, i max = 5a, and f = 250khz (refer to figure 12). the inductance value is chosen frst based on a 30% ripple current assumption. the highest value of ripple current occurs at the maximum input voltage. connect a 160k resistor between the freq/pllfltr and gnd pins, generating 250khz op eration. the minimum inductance for 30% ripple current is: ?i l = 1 f ( ) l ( ) v out 1 ? v out v in ? ? ? ? ? ? a 4.7h inductor will produce 28% ripple current and a 3.3h will result in 40%. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 6a, for the 3.3h value. increasing the ripple current will also help ensure that the minimum on-time of 90ns is not violated. the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f ( ) = 1.8v 22v 250khz ( ) = 327ns the r sense resistor value can be calculated by using the maximum current sense voltage specifcation with some accommodation for tolerances. r sense 50mv 6a = 0.0083 choosing 1% resistors: r1 = 25.5k and r2 = 32.4k yields an output voltage of 1.816v. a pplica t ions i n f or m a t ion the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fds6982s dual mosfet results in: r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t (estimated) = 50c: p main = 1.8v 22v 5 ( ) 2 1+ 0.005 ( ) 50 c ? 25 c ( ) ? ? ? ? ? 0.035 ( ) + 22v ( ) 2 5a 2 ? ? ? ? ? ? 2 ( ) 215pf ( ) ? 1 5 ? 2.3 + 1 2.3 ? ? ? ? ? ? 250khz ( ) = 185mw a short-circuit to ground will result in a folded back cur - rent of: i sc = 29mv 0.0125 C 1 2 90ns 22v ( ) 3.3h ? ? ? ? ? ? = 2.02a with a typical value of r ds(on) and = (0.005/c)(25c) = 0.125. the resulting power dissipated in the bottom mosfet is: p sync = 22v 22v 2.02a ( ) 2 1.125 ( ) 0.022 ( ) = 101.0mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature. c out is chosen with an esr of 0.02 for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.02 (2a) = 40mv p-p
ltc3851a-1 26 3851a1fa typical a pplica t ions figure 12. 1.8v/5a converter from design example with pulse skip operation figure 11. high effciency 3.3v/15a step-down converter mode/pllin freq/pllfltr run tk/ss i th v fb sense ? sense + v in tg boost sw intv cc bg gnd pgood ltc3851a-1 c ss 0.1f c5 0.047f c b 0.1f c c2 330pf c c 2200pf r freq 82.5k r c 15k 30.1k v out 3.3v 15a c15 47pf 4.7f v pull-up + c out 330f 2 c in 22f m1 hat2170h m2 hat2170h c out : sanyo 6tpe330mil c in : sanyo 63hvh22m l1: vishay ihlp5050-ezerr68m01 3851a1 f11 d b cmdsh05-4 r2 154k 1% r1 48.7k 1% v in 4.5v to 32v l1 0.68h r27 3.01k r pg c20 0.1f + mode/pllin freq/pllfltr run tk/ss i th v fb sense ? sense + v in tg boost sw intv cc bg gnd pgood ltc3851a-1 c ss 0.1f c b 0.1f c c2 220pf c c 470pf 0.1f r freq 160k r pg r c 33k r sense 0.01 v out 1.8v 5a 1000pf 4.7f v pull-up + c out 150f 6.3v 2 panasonic sp c in 22f 25v m1 fds6982s m2 fds6982s c out : panasonic eefueog151r c in : marcon thcr70le1h226zt l1: panasonic etqp6f3r3hfa r sense : irc lr 2010-01-r010f 3851a1 f12 d b cmdsh-3 r2 32.4k 1% r1 25.5k 1% v in 4.5v to 22v l1 3.3h +
ltc3851a-1 27 3851a1fa ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691) p ackage descrip t ion 3.00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 0.00 ? 0.05 (ud16) qfn 0904 recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) 2.10 0.05 3.50 0.05 0.70 0.05 0.25 0.05 0.50 bsc package outline
ltc3851a-1 28 3851a1fa p ackage descrip t ion mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev c) msop (mse16) 0910 rev c 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref
ltc3851a-1 29 3851a1fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 5/11 added h-grade and mp-grade parts. refected througout the data sheet. 1-30
ltc3851a-1 30 3851a1fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0511 rev a ? printed in usa r ela t e d p ar t s part number description comments ltc3854 small footprint wide v in range synchronous step-down dc/dc controller fixed 400khz operating frequency, 4.5v v in 38v, 0.8v v out 5.25v, 2mm = 3mm qfn-12 ltc3878 no r sense ? constant on-time synchronous step-down dc/dc controller very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.8v v out 0.9v in , ssop-16 ltc3879 no r sense constant on-time synchronous step-down dc/dc controller very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.6v v out 0.9v in , msop-16e, 3mm = 3mm qfn-16 ltc3850/ltc3850-1 ltc3850-2 dual 2-phase, high effciency synchronous step-down dc/dc controllers, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 780khz, 4v v in 30v, 0.8v v out 5.25v ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 750khz, 4v v in 24v, v out up to 13.5v ltc3834/ltc3834-1 low i q , synchronous step-down dc/dc controller phase-lockable fixed operating frequency 140khz to 650khz, 4v v in 36v, 0.8v v out 10v, i q = 30a, lt ? 3845a low i q , high voltage synchronous step-down dc/dc controller adjustable fixed operating frequency 100khz to 500khz, 4v v in 60v, 1.23v v out 36v, i q = 30a, tssop-16 ltc3775 high frequency synchronous voltage mode step-down dc/dc controller synchronizable fixed frequency 250khz to 1mhz, t on(min) = 30ns, 4v v in 38v, 0.6v v out 0.8v in , msop-16e, 3mm = 3mm qfn-16 typical a pplica t ion 1.5v/15a synchronized at 350khz mode/pllin freq/pllfltr run tk/ss i th v fb sense ? sense + v in tg boost sw intv cc bg gnd pgood ltc3851a-1 c ss 0.1f c1 1000pf c b 0.1f c c2 100pf c c 1000pf r5 1k c2 0.01f pllin 350khz r c 7.5k r22 10 r20 10 r sense 0.002 v out 1.5v 15a 1000pf r pg v pull-up + c out 330f 2 c in 180f m1 rjk0305dpb m2 rjk0301dpb c out : sanyo 2r5tpe330m9 l1: sumida cep125-or6mc 3851a1 ta03 d b cmdsh-3 4.7f r2 43.2k 1% r1 20k 1% v in 6v to 14v l1 0.68h + c10 33pf

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